Integrated circuits comprise many transistors and the electrical interconnections between them. Depending upon the interconnection topology, transistors perform Boolean logic functions like AND, OR, NOT, NOR and are referred to as gates. Some fundamental anatomy of an integrated circuit will be helpful for a full understanding of the factors affecting the flexibility and difficulty to design an integrated circuit. An integrated circuit comprises layers of a semiconductor, usually silicon, with specific areas and specific layers having different concentrations of electron and hole carriers and/or insulators. The electrical conductivity of the layers and of the distinct areas within the layers is determined by the concentration of dopants that are ions implanted into these areas. In turn, these distinct areas interact with one another to form the transistors, diodes, and other electronic devices. These devices interact with each other by field interactions or by direct electrical interconnections. Openings or windows are created for electrical connections through the layers by an assortment of processing techniques including masking, layering, and etching additional materials on top of the wafers. These electrical interconnections may be within the semiconductor or may lie above the semiconductor areas and layers using a complex mesh of conductive layers, usually of metal such as aluminum, tungsten, or copper fabricated by deposition on the surface and then selectively removed. Any of these semiconductor or connectivity layers may be separated by insulative layers, e.g., silicon dioxide.
Integrated circuits and chips have become increasingly complex, with the speed and capacity of chips doubling about every eighteen months because of the continuous advances in design software, fabrication technology, semiconductor materials, and chip design. An increased density of transistors per square centimeter and faster clock speeds, however, make it increasingly difficult to design and manufacture a chip that performs as actually desired. Unanticipated and sometimes subtle interactions between the transistors and other electronic structures may adversely affect the performance of the circuit. These difficulties increase the expense and risk of designing and fabricating chips, especially those that are custom designed for a specific application. The demand for complex custom-designed chips has increased along with the demand for microprocessor-driven applications and products, yet the time and money required to design chips have become a bottleneck to bring these products to market. Without an assured successful outcome within a specified time, the risks have risen with the costs, and the result is that fewer organizations are willing to attempt the design and manufacture of custom chips.
More powerful specialized software tools intended to design chips correctly and efficiently have been introduced to meet the challenge. As the software tools evolve, however, the tools themselves have become increasingly complex requiring more time to master and use them. Correspondingly, the cost of staffing, training, and coordinating the various aspects of chip design has also increased. One general response to this dilemma has been a call for what are termed “higher levels of abstraction,” which simply means that the logical entities with which designers work are standardized and encapsulated into “black boxes” or modules. The software tools used to design chips, nevertheless, are so complex that it is difficult to adapt them to this higher level of abstraction. Coordinating these realms of complexity is a challenge in the design and fabrication of a custom chip. Customer needs and specifications must be aligned with tools and capabilities of both designers and fabrication facilities having their own design rules, equipment, molds, recipes and standards that have myriad implications for the final work and, for best practices, must be considered early in the process.
Meanwhile, several types of chips have been developed that take advantage of this modular approach; they are partly fixed and partly programmable/customizable. The utility of these chips is determined by factors such as complexity, cost, time, and design constraints. Field programmable gate array (FPGA) refers to a type of logic chip that can be easily reprogrammed in the field and the modifications are trivial. FPGAs, however, are very large and expensive. Another disadvantage of FPGAs is their relatively high cost per function, relatively low speed, and high power consumption. FPGAs are used primarily for prototyping integrated circuit designs and once a design is set, faster hard-wired chips are produced. Programmable gate arrays (PGAs) are also flexible in the numerous possible applications that can be achieved but not quite as flexible as the FPGAs, and are more time-consuming to modify and test. An application specific integrated circuit (ASIC) is another type of chip designed for a particular application. ASICs efficiently use power compared to FPGAs and are quite inexpensive to manufacture at high volumes. ASICs, however, are very complex to design and prototype because of their speed and quality. Application specific standard products (ASSPs) are hard-wired chips that meet a specific need but this customization is both time-consuming and costly. An example of an ASSP might be a microprocessor in a heart pacemaker.
A difficult optimization and construction problem is that of constructing these and other various registers and internal memory arrays required for any of many distinct designs. Integrated circuits have either an embedded or external central processing unit (CPU) connected to various registers and memory, either or both of which may be located on or off-chip. On-chip, these registers and memories may be logically and/or physically arranged in various modules throughout the integrated circuit. The registers/memory may be read and written by the CPU through memory-mapped accesses connecting the registers/memory and the CPU using at least one internal bus. Today, chip designers and testers manually and separately define the specification and address map for registers and internal memory, as well as separately and manually specify the register transfer logic (RTL) implementation, the verification testcases, and the firmware header file. This approach is time consuming, tedious, and prone to errors created by manual editing. Maintaining consistency with all the minute changes is very difficult.
Because the invention herein facilitates the use of registers of an integrated chip, it may be useful to present a brief discussion of how registers are used in semiconductor products. Registers are a collection of memory elements having a defined and repeatable purpose; if addressable, each element of the register can be individually accessed by an address. Registers may be configured as “read-only” in that the register stores a value indicating, e.g., a state or status. A register may also be a “read-write” register meaning that the value stored in the register element may be observed and modified. A register may also be a “write-only” register meaning that the address associated with the register element monitors an internal change but the values cannot be observed. Writing to a register, moreover, may store or set bits to a particular value in the register; or writing may clear bits or values within the register. Setting or clearing bits within a register, moreover, may further trigger a counter that may affect an operation elsewhere on the integrated circuit when a threshold value in the counter is reached.
In addition to the above capabilities, it is often convenient to specialize a register to be a control register connected to deeper internal logic of the configurable integrated circuits. An example of a control register is the counter. As internal events occur, the counter changes values. When a read and/or a write operation occur, the value of the counter may be returned and optionally, may be reset. A single counter register can be configured to respond to multiple addresses possibly with a different effect for each address. Another specialized register is the status register whose bits are also driven by internal events. A status register is often associated with a mask register. The combination of a status and a mask register may produce a single output bit when both an internal signal and a mask/enable bit are set. This single output bit is often used as an interrupt bit to notify another subsystem of an event. Another entity using a master interface could then read the status register to determine which bit was set. The combination of status and mask registers is often used for edge-sensitive or level-sensitive operation wherein the edge-sensitive operation can be latched until read and/or the level-sensitive operation passes an internal logic value specified by a signal name. Another specialized register is the most significant bit (MSB) register. When a combination of a mask/enable bit and a status bit are arranged in priority order the MSB register can be read to determine the offset of the most significant bit that is set and enabled. This value can be optionally combined with a base offset and multiplier, both of which may be separate registers, to act directly as an interrupt vector in a processor subsystem. Using a MSB register, reading a single bit can provide the address of the interrupt handling routine to process the status bit that was activated and enabled. Such specialized registers are not easily implementable or testable, and as such, are often referred to as performance-enhancing registers.
There is thus a need in the industry to increase the reliability and the flexibility of the design process of addressable registers and internal memories within the integrated circuits yet at the same time reduce the cost of each individual design